VTU 5th Semester Notes - VTU ECE Notes 10AL51 Management and Entrepreneurship Notes 10EC52 Digital Signal Processing Notes 10EC53 Analog Communication Notes 10EC54 Microwaves and Radar Notes 10EC55 Information Theory & Coding Notes 10EC56 Fundamentals of CMOS VLSI Notes VTU 6th Semester Notes - VTU ECE Notes 10EC61 Digital Communication Notes.

Vlsi design notes(1st unit) according to vtu syllabus.(BE) • 1. 1 VLSI Design UNIT -1 Introduction to MOS technology  Moore’s law  Speed- power performance  nMos fabrication  CMOS fabrication  n-well process  p-well process  BiCMOS  Comparison of bipolar and CMOS • 2 1 INTRODUCTION  Integrated circuit (IC):- an IC is a combination of interconnection circuit elements on a continuous substrate.

 Substrate:- substrate is a supporting material upon which an IC is fabricated.  Wafer:- a wafer is a basic physical unit used in processing. It usually contains large number of identical IC’s.  Transistor was invented in 1947.  The very first IC emerged at the beginning of 1960.

PART-A Basic MOS Technology Integrated circuits era, enhancement and depletion mode MOS transistors. NMOS fabrication. CMOS fabrication, Thermal aspects of processing, BiCMOS technology, production of E-beam masks. 3 Hours MOS transistor theory Introduction, MOS device design equations. Unit-2: Circuit Design Processes MOS layers, stick diagrams, Design rules, and layout- lambda-based design and other rules. Examples, layout diagrams, symbolic diagram, tutorial exercises.

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Basic physical design of simple logic gates. Unit 3: CMOS Logic Structures CMOS complementary logic, BiCMOS logic, Pseudo-nMOS logic, Dynamic CMOS logic, clocked CMOS logic, Pass transistor logic, CMOS domino logic cascaded voltage switch logic (CVSL). Unit-4: Basic circuit concepts Sheet resistance, area capacitances, capacitances calculations. The delay unit, inverter delays, driving capacitive loads, propagation delays, wiring capacitance Scaling of MOS circuits Scaling models and factors, limits on scaling, limits due to current density and noise. PART-B Unit-5: CMOS subsystem design Architectural issues, switch logic, gate logic, design examples-combinational logic, clocked circuits. Other system considerations. 3 Hours Clocking strategies Unit-6: CMOS subsystem design processes General considerations, process illustration, ALU subsystem, adders, multipliers.

Unit-7: Memory registers and clock Timing considerations, memory elements, memory cell arrays Unit-8: Testability Performance parameters, layout issues I/O pads, real estate, system delays, ground rules for design, test, and testability.